I use NativeLink sparsely and I don't have the tools at hand to confirm. I found an example for simulation with native-link and ModelSim-Altera in Verilog (Native_Modelsim_restored : multiplier project) and tried it with no problem for RTL and gate level simulation, so it seem's that it is not a problem with my version of Quartus. Run simulation until all vector stimuli are used : on.Design instance name in test bench : selector.Use test bench to perform VHDL timing simulation : on.top level module in test bench : selector_test.The Settings/EDA Tool Settings for simulation are : The main strange thing is that the RTL simulation (trough the menu tools/run simulation eda tool/ eda rtl simulation ) is functional without warning. I had the sub-repertory simulation/modelsim. I put in attach file a zip, with the selector project, selector vhdl file and selector_test vhdl file. I had read such informations in the forum and Altera's documentation, but this files have been created by the EDA Tools (or the simulator, i don't know) in the sub-repertory simulation/modelsim. You need both file files for the simulation.
_vhd.sdo ( this file contains the timing information)Ģ.vho ( this file contains your design gatelevel) Quartus generates two files for the modelsim simulation.ġ. selector_run_msim_gate_vhdl.do PAUSED at line 12 # ** Error: (vsim-SDF-3894) : Errors occured in reading and resolving instances from compiled SDF file(s). # ** Error: (vsim-SDF-3250) selector_vhd.sdo(0): Failed to find INSTANCE '/selector'. # Loading instances from selector_vhd.sdo What i forgot in the settings of Quartus II to use this new EDA-Tools (for me !) # Loading instances from selector_vhd.sdo# ** Error: (vsim-SDF-3250) selector_vhd.sdo(0): Failed to find INSTANCE '/selector'.# ** Error: (vsim-SDF-3894) : Errors occured in reading and resolving instances from compiled SDF file(s).# ** Error: (vsim-SDF-3250) selector_vhd.sdo(0): Failed to find INSTANCE '/selector'.# Error loading design# Error: Error loading design # Pausing macro execution # MACRO. I’ve no problem with the RTL simulation, but some ones with the gate level ones.Modelsim (ModelSim Altera starter edition 6.5e) write in the transcript aera : The EDA Tool settings for simulation are turned on ModelSim-Altera, with VHDL format.
After the proposed modification in the Assignments Settings menu (Format for output netlist è vhdl, Map illegal HDL character è on, Compile test bench è T1 for the use of the benches file : “selector_test.vhd”. I’ve reduced my problem to the smallest ones to simulate one selector (selector.vhd). I have readed Quartus Handbook and Help, lot of threads in the Forum but I did’nt found the answer. I'm new with the ModelSim-Altera (i' known well Max+Plus II and the embedded version of simulation in the previous version of Quartus).